Electronic control system for sewing machines

ABSTRACT

A first memory stores stitch control signals. A second memory stores these signals temporarily and reads them out to enable stitches to be formed. As a pattern is stitched, the first memory is readdressed and stitch control signals are successively written into and read out of the second memory. In one embodiment, the second memory is a RAM--in a second embodiment, the second memory is a shift register. Monostable multivibrators are used to operate the memories.

BRIEF DESCRIPTION OF THE INVENTION

This invention relates to an electronic control for a sewing machine ofthe type which has a pattern forming device for stitching patterns byvarying relative positions of the fabric to be stitched and the needle.More particularly, this invention relates to an electronic controlsystem for a sewing machine which is of simple structure and is able tostitch a large number of patterns.

It is, therefore, a primary object of the invention to store fixedpattern stitch control signals in a first semiconductor memory, and toproduce many patterns without being limited to the signals so stored, byproviding a second semiconductor memory for receiving signalstransferred from the first semiconductor memory or from external sourcessuch as magnetic tape or punch cards.

It is a second object of the invention to carry out exact electroniccontrol of such sewing machine by means of a relatively simplifiedcircuit structure.

The other features and advantages of the invention will be apparent fromthe following description of the invention in reference to the preferredembodiments as shown in the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a sewing machine in which the present invention isinstalled; and

FIGS. 2A-B and 3A-B are block diagrams of two preferred embodiments ofthe invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

In FIG. 1 reference numeral 1 is a machine housing, while referencenumeral 2 is an upper shaft of the sewing machine driven by a machinemotor (not shown) for vertically reciprocating needle bar 3 and needle4.

The reference figure PG is a pulse generator which is synchronized withthe upper shaft 2 to produce periodic pulses. Pulse generator PG iscomposed, as is generally known, of a U-shaped element 5 secured tomachine housing 1 and carring a light-emitting diode (not shown), aphototransistor (not shown) opposite thereto, and a photo-interrupter 6secured to upper shaft 2 and rotating therewith. Thus, pulse generatorPG issues one positive signal for each rotation of upper shaft 2 whenneedle 4 is positioned above a needle plate (not shown). SW₁ -SW₅ arepattern selecting switches, and 7 is a control system, 8 is a pulsemotor for needle bar 3 laterally connecting rod 9 during rotation ofpulse motor 8. Numeral 10 is a pulse motor for feeding the fabric, andcontrols horizontal movement of feed dog 16 via link 11, feed adjuster12, fork rod 13, connecting link 14 and a horizontal feeding shaft 15.Numeral 17 is a lower shaft of the sewing machine. Lower shaft 17rotates in synchronism with upper shaft 2 to rotate a loop taker (notshown).

FIGS. 2A-2B are a block diagram of a first embodiment of the invention,which is shown at 7 in FIG. 1. PS is a pattern selecting deviceincluding pattern selecting switches SW₁ -SW₅ shown in FIG. 1. When apattern is selected, that pattern is latched into latch circuit L₁ inthe form of a 3-bit encoded signal. MM₁ is a monostable multivibratorwhich receives a selection control signal from pattern selecting devicePS, and issues a signal in response. C₈, used throughout, denotes a gateterminal of that element in which it is shown. ROM is an electronicread-only memory storing stitch control signals, which has 8 addressterminals D₁ -D₄ and 16 output terminals E₁ -E₃. E₁ outputs 6 bits forsuccessively addressing ROM itself, E₂ outputs 5 bits for controllingfabric feed, and E₃ outputs 5 bits for swinging needle 3. MP₁ is amultiplexer having a mode input terminal M. Multiplexer MP₁ connectsterminal D2 of memory ROM to an input signal at A issued from latchcircuit L₁ when mode input terminal M is logically high and connectsterminal D2 to an input signal at B issued from timing buffer TB whenmode input terminal M is logically low. Timing buffer TB receives theaddress changing output at terminals E₁ and addresses inputs D₁ and D₂of memory ROM. Timing buffer TB is reset when it receives at resetterminal R a pattern selection signal via OR gate OR₁, which signal isgenerated by monstable multivibrator MM₁. Timing buffer TB then receivesan astable signal from monostable multivibrator MM₄ via OR-gate OR₂ andsuccessively transmits the address changing signal at terminals E₁ toaddress input terminals D₁ and D₂ each time the astable signal fallsprior to actual stitching. Read-only memory ROM then transfers all thesignals of the selected pattern which appear at terminals E₂ and E₃ to arandom access memory RAM. The oscillation velocity of the astable signalfrom monostable multivibrator MM₄ is, therefore, the readout velocity ofread-only memory ROM. FF₁ and FF₂ are flip-flops and receive the outputof monostable multivibrator MM₁ at their set terminals S. Flip-flop FF₁receives the astable signal from monostable multivibrator MM₄ at itsreset terminal R, and has an its output Q connected to the mode input Mof multiplexer MP₁. Flip-flop FF₂ has a true output Q connected to anenable terminal OE_(M) of read-only memory ROM. Therefore, flip-flop FF₂is set by the pattern selection signal from monostable multivibrator MM₁to activate read-only memory ROM and to read out the data therein. MM₂,MM₃, and MM₄ are monostable multivibrators each connected, via OR gateOR₃, to the output of MM₁ and are triggered on negative flanks ofsignals thereat. Monostable multivibrator MM₃ has an output connected towrite-in terminal W of memory RAM, and monostable multivibrator MM₄ hasan output connected to one input of AND-gate AND₁. True output Q offlip-flop FF₂ is connected to another input of AND₁ and is connected toan input terminal of monostable multivibrator MM₂ via OR-gate OR₃. ThusMM₂, MM₃, and MM₄ begin oscillating upon negative flanks of the signalfrom monostable multivibrator MM₁, and continue during the set period offlip-flop FF₂. Flip-flop FF₁, receiving the oscillating signal from MM₄at resetting terminal R, is set by a pattern selecting signal from MM₁,and is reset by the following signal from MM₄. Thus, just after thepattern selection, the multiplexer MP₁ is caused route the signal atterminal A of the latch circuit L₁ to address terminal D₂ of the ROM.Thereafter, multiplexer MP₁ is caused to similarly route the signal atterminal B, which signal is successively issued via timing buffer TB. Ofthe address signals for reading out an initial stitching signal of thepattern, the data at terminals D₁ are all initially 0. The addresschanging signal at terminals E₁, as compared with the final stitchingsignal has, at this time, an uppermost 1 bit which is identical with thesignal at input A of the multiplexer MP₁, all other bits being 0.AND-gate AND₃ receives an output signal from exclusive OR-gate ExOR fordetecting whether or not these signals are the same, and likewisereceives an output from AND-gate AND₂ for detecting whether or not theyare both 0. AND₃ is connected to resetting terminal R of flip-flop FF₃via OR₄ and AND₄ (which is also connected at an input to the output ofMM₄) and resets the flip-flops when ROM reads out the final stitchingsignal. FF₃ is a flip-flop which is reset together with flip-flop FF₂.The output of AND-gate AND₅ (which has inputs connected to complementoutputs Q of FF₂ and FF₃) is connected to an input of MM₅. The output ofMM₅ is connected to the resetting terminals R of MM₂, MM₃ and MM₄ andalso is connected to the other input of OR₁ so as to reset MM₂, MM₃ andMM₄ and the timing buffer TB when the final stitching signal isproduced. C is a counter, and the output of AND₆ (which has inputsconnected to the output of OR₄ and the output of MM₃) and the output ofAND₅ are both connected to its resetting terminal R via OR₅. Counter Cis counted up by output of MM₂, and its 6-bit output is connected to theaddress changing terminals C₁ of the RAM to be stored matching patterninput data of inputs F₂ and F₃ of RAM, as well being connected to theaddress signal terminal G of RAM via latch circuit L₂ and multiplexorMP₂, so that the counter C may write in the RAM. Latch circuit L₂receives the outputs of AND₅ and MM₄ via OR₆ at its gate terminal C_(p).The multiplexer MP₂ receives the output of AND₅ at its mode input M, andwhen mode input M is logically low, MP₂ transmits the signal at inputsC₂ from counter C to serve as an address signal at G for writing in RAM.When mode input M is logically high, MP₂ transmits at inputs H'₁ fromthe 6 bit output H₁ of RAM for use as an address signal to G. RAMoperates substantially the same as does ROM in readout mode, and timingbuffer TB is used both with ROM and with RAM. However, at their gateinputs, ROM receives the astable signal from MM₄, while RAM receivessignals from pulse generator PG (shown in FIG. 1) via OR₃. Terminals H₂and H₃ of 5 bits each are connected to pulse motor driving device DV todrive it with stitching signals which are produced in the same order asthe fabric feed controlling signals from outputs E₂ or K₂ and needleswinging amplitude signals from E₃ or K₃, i.e. from ROM or an externalmemory reader device ExR. OE_(A) of RAM is an enable terminal connectedto the output of AND₅ so as to read out the RAM when OE_(A) is logicallyhigh. ExR is an external memory reader which employes magnetic tape orpunch cards, and 5 bit stitching signal outputs K₂ and K₃ are connectedto outputs E₂ and E₃ of ROM and thus to inputs F₂ and F₃ of RAM.Terminal RD carries a readout signal which is produced in response tomanual operation when reader ExR is used, and this readout signal isdelivered to set terminal S of FF₃. True output terminal Q of FF₃ isconnected to the terminal OE_(X) of RAM, and manual operation causes areadout of ExR and a write in of RAM until such readout ceases, as isthe case with the ROM. SY is a synchronous signal output terminal whichcarries a signal generated in response to each of the stitching signals.This signal is delivered to an input of OR₃ so as to cause MM₂, MM₃, MM₄to issue a one shot pulse each time the signal is produced, so as tocount up counter C and to activate terminal W of RAM and latch circuitL₂. END is an ending signal output terminal matched with said stitchingsignals K₂, K₃ for recognizing end of readout by detecting an 11th bitof data, and is connected to an input of OR₄. END is reset along withFF₃, by the ending signal matching control signal of the final stitch soas to stop readout of ExR and write in into the RAM.

In this first embodiment when any of the pattern selecting switches SW₁-SW₅ in pattern selector PS is operated in order to stitch thecorresponding pattern according to data stored in ROM, a 3 bit codedesignating the pattern is produced, and this code is latched into latchcircuit L₁ while MM₁ operates FF₁ sets and multiplexer MP₁ transmits a 3bit address code to inputs D₂, D₃ and D₄ of ROM to serve as a patterncode. Since TB is reset via OR₁, the address bits at D₁ of ROM are all0, and the code composed of the address data at D₁, D₂, D₃ and D₄ is setto generate the initial stitching signals at E₂ and E₃, with FF₂ beingconcurrently set for producing the address signal for reading out thesecond addressing signal at E₁ to cause the enable terminal OE_(M) toreadout the ROM. The pattern selecting signal causes MM₂ to issue a oneshot pulse via OR₃ and counts counter C to a decimal code 1 on thenegative pulse flank. This makes the address changing date at C₁ matchthe initial stitching signals E₂ and E₃ of the RAM for addressing thenext (i.e. the second) stitch. MM₃ issues a one shot pulse at thenegative flank of the pulse from pulse terminal W of the RAM, beginningwrite in. The address data at G is all 0's at this time, since modeinput M of MP₂ is at logically low via AND₅ and does not receive thegate signal at Cp of latch circuit L₂, and the address data at G storesa signal which matches the initial stitching signal and the 2nd stitchaddressing signal at the 0 address. Subsequently, MM₄ issues a one shotupon a negative flank of the pulse from MM₃. FF₁ is thus reset by thissignal and MP₁ transfers the data at B (which has passed through TB) toinput D₂ of ROM. Latch circuit L₂ receives the gate signal at Cp via OR₆and latches decimal code 1 from the counter C, to cause the address dataat G of RAM to correspond to an address of 1. The rising output signalfrom MM₄ gives a signal to the gate Cp of TB and transfers theaddressing signals E₁ for the 2nd stitch to address terminals D₁ and D₂of ROM. A match of the signals at address terminals D₁ and D₂ andsignals at D₃ and D₄ from PS forms an address signal for reading out the2nd stitch signals at E₂ and E₃ and the addressing signal to the thirdstitch. MM₂ then issues another one shot pulse via AND₁ and OR₃ upon thenegative flank of the output signal from MM₄. Subsequently MM₂, MM₃ andMM₄ successively advance one shot pulses and repeat them to read out theROM write in RAM. The address changing signal at E₁ coincides at itsuppermost bit with the lowest bit from latch circuit L₁. ROM reads outfinal stitching signals at E₂ and E₃ in accordance with the addresssignals appearing at D₁ and D₂, which address signals pass through TB asthe output signal from MM₄ rises. Since the lower 5 bits at E₁ remain 0,the output of AND₂ is brought logically high. Moreover, the output ofExOR is low, so that the output of AND₃ goes high and the output of OR₄goes logically high.

Meanwhile, the output from MM₄ drops, causing the output of MM₂ to drop,causing counter C to count up one count. A subsequent pulse from MM₃resets counter C via AND₆ and OR₅, since the output of OR₄ is stilllogically high. Thus, the data appearing at RAM inputs C₁ is all zero.Since terminal W of RAM is logically high, RAM is placed in the writeinmode, and the latter serves as an initial stitch addressing signalenabling the data at ROM outputs E₂ and E₃ to be written into RAM. Asubsequent output signal from MM₄ resets FF₂ and FF₃ via AND₄ (whichreceives the logically high output of OR₄), resets MM₂, MM₃ and MM₄ viaAND₅ and MM₅, and further resets TB via OR₁ so that transfer of datafrom ROM to RAM is completed. The high output of AND₅ is delivered toenable terminal OE_(A) of RAM to cause RAM to operate in the readoutmode. The high output of AND₅ is delivered via OR₅, to terminal R ofcounter C, to reset counter C and to start writein in RAM.

The ending of such writein causes RAM to give an initial stitch controlsignal to the pulse motor driving device DV. The mode of the multiplexerMP is changed by the logically high output of AND₅ and the addresssignal at G of RAM turns into a signal passing through TB, but TBdesignates the 0 address upon resetting and issues an output of aninitial stitching signal. When the sewing machine is driven, the pulsegenerator PG issues one pulse for early rotation of the sewing machine,and the timing buffer TB transfers addressing data at H₁ of RAM to theaddressing terminal G upon each rotation to advance the stitchingsignals at H₂ and H₃. When the stitching pattern is finished, thepattern i- returned to its initial state, and TB repeatedly delivers astitch controlling signal to the pulse motor driving device DV so as todrive the pulse motors 10 and 8 for controlling the needle swing andfabric feed.

With respect to the data transfer to RAM from the external storingdevice ExR, for reading magnetic tape or punched cards when the readeris operated, the readout command signal at RD sets FF₃ and gives asignal to the enable terminal OE_(X) to make the pattern controllingsignals at K₂ and K₃ available to RAM. When the pattern controllingsignal is produced, the synchroneous signal SY is produced synchronouslytherewith to cause MM₂, MM₃ and MM₄ to issue one shot pulses insuccession. ExR like ROM during readout, stores only one stitchingsignal, and a subsequent signal at SY causes a following stitchingsignal to be stored, and when storage of all the stitches is finished anend signal at END resets FF₃ via OR₄ to finish readout operation andwritein in RAM, so that RAM can subsequently be read out.

The second embodiment of the invention shown in FIG. 2 employes therandom access memory RAM for temporary storage, while the secondembodiment uses a shift register SR. Parts common to those in FIG. 2 aredesignated with the same reference characters and explanation thereofwill be omitted. ROM is read out in the same fashion as in FIG. 2. Forsimplicity the 5 bit pattern control signal terminals E₂ and E₃ andterminals connected thereto are shown as one terminal and one connectingline. SR is a shift register in which input terminals V₂ and V₃ of 5bits each receive stitch control signals from E₂ and E₃ of ROM andstitching control signals from K₂ and K₃ of ExR. SR is composed ofparallel connections of 11 bits between input terminals V₂ and V₃,output terminals W₂ and W₃ (of 5 bits each) an input terminal V₁ fordetermining whether or not data entering from input terminals V₂ and V₃are stitching signals, and output terminal W₁. The shift register has aresetting terminal R receiving an output signal from MM₁ and from RD ofExR via OR₇, and also has a shift pulse input terminal Cp. Outputterminals W₁, W₂ and W₃ provide 11-bit data to input terminals V₁, V₂and V₃, and the signals at terminals W₂ and W₃ compose the stitchcontrol signal and are connected to DV via a latch circuit L₃. Shiftregister ST of the input terminals V₁, V₂, V₃ and the output terminalsW₁ , W₂, W₃ of respective 11 tracks at both sides, has the bit number(step number) which is more than the maximum stitch number of thepattern to be selected and is the same number. Shift register SR storesthe pattern signals E₂ and E₃ or K₂ and K₃ at the shift pulse terminalCp, and receives the output of MM₄ via OR₈ in order to shift saidpattern signals. AM is an astable multivibrator whose enable terminalOE₀ receives the output signal at W₁ or SR via inverter IN so as tooscillate when output W₁ is logically low that is, when the signals arenot stitching signals. AND₇ receives both an input signal to and anoutput signal from AM the output from AND₅, and provides a signal toshift pulse terminal Cp of shift register SR via OR₈. This constructionshifts the data stored in SR until output W₁ goes logically high, i.e.until signals at W₂ and W₃ respond to stitching signals, after the datatransfer from ROM to SR is complete and the output of AND₅ becomeslogically high. The output of the pulse generator PG is rated to MM₆ viaAND₈ (which also receives the output signal from AND₅ at its otherinput), and causes a shift signal to appear at shift pulse terminal Cpof shift register SR via OR₈ so as to shift the signal within shiftregister SR each time the sewing machine rotates to saw a stitch. AND₉receives both the output signal from AND₅ and the signal at W₁ of SR,and when the signal at W₁ is high, AND₉ causes latch circuit L₃ todeliver the signals at W₂ and W₃ SR to DV.

In the embodiment shown in FIG. 3, the output of MM₁ (determined inaccordance with operation of pattern selector PS) resets TB via OR₁ andresets shift register SR via OR₇. The rising flank of a first signalfrom MM₄ provides a shift pulse to SR via OR₈, and simultaneously causesa logically high signal to appear at input terminal V so as to store itin first bit cell and to thereby store, at that 0 address stitchingsignals at E₂ and E₃ for a first stitch which latter signal appears atinput terminals V₂ and V₃. Due to the rising signal of MM₄, the outputsat E₂ and E₃ of ROM become signals for a second stitch, and upon receiptof a subsequent rising signal from MM₄, the signal stored in the firstbit cell is shifted to a second bit cell, and the first bit cellcorresponding to terminals V₁, V₂ and V₃ of shift register SR stores thefirst and second stitching signals as a stitching signal for a secondstitch. This shifting is repeated in succession, and when the logicallyhigh signal and the final stitching signal are stored in the first bitcell, the signal for the first stitch and the first stitching signal areshifted by the stitching number composed of the stitch pattern. Sincethe step number of the shift register SR is increased higher than thisstitching number, these signals do not reach output terminals W₁, W₂ andW₃. When ROM issues the output of the final stitching signal, FF₂, FF₃,TB, MM₃ and MM₄ are reset, the signal at OE_(N) of ROM becomes low andROM accordingly, becomes inoperative. The output of AND₅ is thenlogically high. When a signal for stitching a seam does not reach outputterminals W₁, W₂ and W₃, terminal W₁ is low, and AM oscillates. Thisoscillation delivers shift pulses to shift register SR via AND₇ and OR₈,and shifts the stitching data until output signal at W₁ becomes high,that is, until the initial stitching signal reaches output terminals W₂and W₃. When the output signal at W₁ becomes high, AM provides a clockpulse to latch circuit L₃ via AND₉, and causes initial stitching signalsat W₂ and W₃ to be delivered to DV. When the sewing machine is rotated,pulse generator PG issues a signal for each rotation, and the shiftregister SR successively shifts the data to advance it to outputterminals W₂ and W₃. When the stitching signal ends and output signal atW₁ becomes low again, AM oscillates to shift shift register SR and toprovide an initial stitch signal for pattern repetition. Thus, stitchpatterns are repeated.

Readout from ExR and from ROM to SR is the same as in FIG. 2, and ROMoperation is carried out here in the same fashion as has been describedthere.

As mentioned above, the present invention enables patterns to be formedby the stitching signals stored in ROM, and also enables patterns storedin ROM, and also enables patterns to be formed by reading magnetic tapeand punched cards in reader ExR. Since address data for ROM are based onthe output data from the ROM, the elements which control readout of ROM,readout of of ExR, operation of RAM, and the writing-in timing to shiftregister SR, may be used in common. Accordingly, the circuit structureis relatively simple and exact in operation.

We claim:
 1. An electronic control system for use in sewing machineswhich vary needle position and fabric feed in order to stitch aplurality of stitch patterns in accordance with stitch control signals,comprising: a pulse generator issuing pulses in synchronism withrotation of the sewing machine; a first memory storing a plurality ofstitch control signals; a user-operable pattern selector for selectingan initial address within the first memory; a plurality of monostablemultivibrators which are connected to each other and to the patternselector in a manner that the monostable multivibrators oscillate whenthe pattern selector is operated; and a second memory connected to thepulse generator, the first memory and said plurality of monostablemultivibrators, the second memory operating in a manner that each timean oscillation of the monostable multivibrators takes place, a stitchcontrol signal is read out of the first memory and temporarily stored inthe second memory, and each time the pulse generator generates a pulse,a stitch control signal temporarily stored in the second memory is readout therefrom and used to vary needle position and fabric feed.
 2. Theelectronic control system defined by claim 1, wherein the first memoryis a read-only memory with 8 address bits.
 3. The electronic controlsystem defined by claim 2, wherein the first memory has 6 first outputterminals for readdressing the first memory, wherein the first memoryhas 5 second output terminals for controlling fabric feed, and whereinthe first memory has 5 third output terminals for controlling needlesewing amplitude.
 4. The electronic control system defined by claim 1,wherein the pattern selector incudes a plurality of user-operablepattern selecting switches, a 3 bit encoder connected thereto, and alatch circuit connected to the encoder, the pattern selector operatingin a manner that when a pattern selecting switch is operated, a 3 bitcode is encoded by the encoder and latched into the latch circuit. 5.The electronic control system defined by claim 1, wherein the pluralityof monostable multivibrators includes a first monostable multivibrator,a second monostable multivibrator, a third monostable multivibrator anda fourth monostable multivibrator, wherein each of the monostablemultivibrators have an input and an output, the output of the firstmonostable multivibrator being connected to an input of an OR-gate, anoutput of the OR-gate being connected to the input of the secondmonostable multivibrator, the output of the second monostablemultivibrator being connected to the input of the third monostablemultivibrator, the output of the third monostable multivibrator beingconnected to the input of the fourth monostable multivibrator, theoutput of the fourth monostable multivibrator being connected to aninput of an AND-gate which has an output connected to another input ofthe OR-gate, the output of the first monostable multivibrator beingfurther connected to the set input of a flipflop which also has anoutput, the output of the flipflop being connected to another input ofthe AND-gate, and the output of the third monostable multivibrator beingfurther connected to the second memory to allow a stitch control signalto be stored therein upon oscillation of the monostable multivibrators.6. The electronic control system defined by claim 3, wherein the secondmemory has 5 second input terminals connected to the second outputterminals of the first memory, wherein the second memory has 5 thirdinput terminals connected to the third output terminals of the firstmemory, wherein the second memory has 5 second output terminals and 5third output terminals whereby fabric feed and needle swing amplitudecan be controlled by the second memory in an order identical to thatorder in which signals appear at the second and third output terminalsof the first memory, and wherein the control system further includes apulse motor driving device connected to the second and third outputterminals of the second memory.
 7. The electronic control system definedby claim 1, wherein the second memory has an enable terminal which isconnected to an output of an AND-gate, and which, when in a logicallyhigh state, causes the second memory to read out stitch control signals.8. The electronic control system defined by claim 1, wherein the secondmemory is an 11 bit shift register with a discriminating input connectedto one of said plurality of monostable multivibrators, thediscriminating input indicating presence of and lack of presence ofstitch control signals at the shift register.
 9. The electronic controlsystem defined by claim 8, wherein the electronic control system furtherincludes a pulse motor driving device controlled by the second memoryvia a latch circuit, and wherein the electronic control system furtherincludes an external reader connected to the second memory for enablingstitch control signals to be introduced from an external source.
 10. Theelectronic control system defined by claim 1, further including a timingbuffer connected to the pulse generator and the second memory, thetiming buffer cyclicly advancing the stitch control signals in responseto receipt of a pulse from the pulse generator, whereby after a stitchpattern is completed the stitch pattern is repeated.
 11. The electroniccontrol system defined by claim 8, wherein the pulse generator isconnected to the shift register and shifts data therein each time thepulse generator generates a pulse, and wherein the electronic controlsystem further includes an astable multivibrator which is connected tothe shift register and oscillates after a stitch pattern is completed,whereby the stitch pattern can be repeated once again.